LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 104
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LPC1857_53
Manufacturer Part Number
LPC1857_53
Description
The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1853FBD208.pdf
(131 pages)
- Current page: 104 of 131
- Download datasheet (2Mb)
NXP Semiconductors
Table 16.
C
[1]
[2]
[4]
LPC1857_53
Objective data sheet
[3]
[5]
Symbol
t
t
t
BLSLBLSH
BLSHEOW
BLSHDNV
Fig 26. External static memory read/write access (PB = 0)
L
= 30 pF, T
Parameters are shown as RD
Parameters specified for 40 % of V
Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).
EMC_BLSx
EMC_CSx
EMC_WE
EMC_OE
EMC_Ax
EMC_Dx
Dynamic characteristics: Static external memory interface
Parameter
BLS LOW to BLS HIGH time WR
BLS HIGH to end of write
time
BLS HIGH to data invalid
time
amb
=
40
[1]
C to 85
n
or WD
C, V
DD(IO)
RD
DD(REG)(3V3)
RD
n
2
in
1
for rising edges and 60 % of V
Figure 26
RD
Conditions
WR
WR12;
PB = 0
All information provided in this document is subject to legal disclaimers.
5
10
11
; PB = 0
; PB = 0
RD
Rev. 1 — 14 December 2011
= <tbd>.
RD
as indicated in the Conditions column.
5
RD
5
4
[1]
[5]
Min
(WAITWR
WAITWEN + 1)
T
<tbd>
<tbd>
cy(clk)
EOR
RD
RD
DD(IO)
6
+ <tbd>
7
for falling edges.
WR
…continued
WR
2
9
32-bit ARM Cortex-M3 microcontroller
Typ
(WAITWR
WAITWEN + 1)
T
<tbd>
<tbd>
cy(clk)
WR
WR
1
10
+ <tbd>
WR
12
WR
LPC1857/53
11
Max
(WAITWR
WAITWEN + 1)
T
<tbd>
<tbd>
cy(clk)
EOW
© NXP B.V. 2011. All rights reserved.
+ <tbd>
WR
002aag214
8
104 of 131
Unit
ns
ns
ns
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