LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 80

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1857_53
Objective data sheet
7.20.4 Internal RC oscillator (IRC)
7.20.5 PLL0USB (for USB0)
7.20.6 PLL0AUDIO (for audio)
7.20.7 System PLL1
7.20.8 Reset Generation Unit (RGU)
7.20.9 Power control
The IRC is used as the clock source for the WWDT and/or as the clock that drives the
PLLs and then the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to
1 % accuracy over the entire voltage and temperature range.
Upon power-up or any chip reset, the LPC1857/53 use the IRC as the clock source.
Software can later switch to one of the other available clock sources.
PLL0 is a dedicated PLL for the USB0 High-speed controller.
PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz
to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.
The audio PLL PLL0AUDIO is a general-purpose PLL with a small step size. This PLL
accepts an input clock frequency derived from an external oscillator or internal IRC. The
input frequency is multiplied up to a high frequency with a Current Controlled Oscillator
(CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the desired
output frequency. The output frequency can be set as a multiple of the sampling frequency
f
range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz. Many other
frequencies are possible as well.
The PLL1 accepts an input clock frequency from an external oscillator in the range of
10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO
operates in the range of 156 MHz to 320 MHz. This range is possible through an
additional divider in the loop to keep the CCO within its frequency range while the PLL is
providing the desired output frequency. The output divider can be set to divide by 2, 4, 8,
or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset. After reset, software can enable the PLL. The program must
configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a
clock source. The PLL settling time is 100 s.
The RGU allows generation of independent reset signals for individual blocks and
peripherals.
The LPC1857/53 feature several independent power domains to control power to the core
and the peripherals (see
timer, the CREG block, the OTP controller, the back-up registers, and the event router)
are located in the RTC power-domain. The main regulator or a battery supply can power
the RTC. A power selector switch ensures that the RTC block is always powered on.
s
to 32f
s
, 64f
All information provided in this document is subject to legal disclaimers.
s
, 128  f
Rev. 1 — 14 December 2011
Figure
s
, 256  f
8). The RTC and its associated peripherals (the alarm
s
, 384  f
s
, 512  f
32-bit ARM Cortex-M3 microcontroller
s
and the sampling frequency f
LPC1857/53
© NXP B.V. 2011. All rights reserved.
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can