LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 71

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1857_53
Objective data sheet
7.15.8.1 Features
7.15.9.1 Features
7.15.8 LCD controller
7.15.9 Ethernet
The LCD controller provides all of the necessary control signals to interface directly to
various color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024  768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of
the displayed data) while still supporting many colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time required to operate the display.
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AHB master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
Supports single and dual-panel color STN displays.
Supports Thin Film Transistor (TFT) color displays.
Programmable display resolution including, but not limited to: 320  200, 320  240,
640  200, 640  240, 640  480, 800  600, and 1024  768.
Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized for color STN and TFT.
24 bpp true-color non-palettized for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM.
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.
LCD panel clock can be generated from the peripheral clock, or from a clock input pin.
10/100 Mbit/s
TCP/IP hardware checksum
IP checksum
DMA support
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 December 2011
32-bit ARM Cortex-M3 microcontroller
LPC1857/53
© NXP B.V. 2011. All rights reserved.
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