LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 98

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
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[4]
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[9]
LPC1857_53
Objective data sheet
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Fig 21. I
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
bridge the undefined region of the falling edge of SCL.
C
The maximum t
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
The maximum t
t
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
A Fast-mode I
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
Standard-mode I
VD;ACK
b
SDA
= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
SCL
2
by a transition time. This maximum must only be met if the device does not stretch the LOW period (t
C-bus pins clock timing
70 %
30 %
S
11.6 I
2
t
C-bus device can be used in a Standard-mode I
f
f
HD;DAT
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
2
C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
t
f
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t
70 %
Table 14.
T
values.
30 %
Symbol
common to input and output
t
t
t
t
2
r
f
WH
WL
amb
S-bus interface
1 / f
= 25
SCL

C; V
Parameter
rise time
fall time
pulse width HIGH
pulse width LOW
Dynamic characteristics: I
t
HD;DAT
70 %
30 %
DD(REG)(3V3)
70 %
30 %
All information provided in this document is subject to legal disclaimers.
f
.
t
SU;DAT
Rev. 1 — 14 December 2011
= 3.3 V. Conditions and data refer to I2S0 and I2S1 pins. Simulated
70 %
30 %
2
Conditions
on pins I2Sx_TX_SCK
and I2Sx_RX_SCK
on pins I2Sx_TX_SCK
and I2Sx_RX_SCK
C-bus system but the requirement t
t
LOW
2
S-bus interface pins
r(max)
t
HIGH
+ t
32-bit ARM Cortex-M3 microcontroller
70 %
30 %
SU;DAT
t
VD;DAT
= 1000 + 250 = 1250 ns (according to the
Min
-
-
<tbd>
-
SU;DAT
IH
LPC1857/53
(min) of the SCL signal) to
= 250 ns must then be met.
Typ
-
-
-
-
LOW
© NXP B.V. 2011. All rights reserved.
) of the SCL signal. If
Max
<tbd>
<tbd>
-
<tbd>
002aaf425
f
is specified at
98 of 131
VD;DAT
Unit
ns
ns
-
ns
or