HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 100

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
3.3 Assigners
The data flow block diagram in Figure 3.1 contains three assigners. These functional blocks
are used to connect FIFOs, HFC-channels and E1 time slots and PCM time slots respectively
with each other.
3.3.1 HFC-channel assigner
The channel assigner functionality depends on the data flow mode described in Section 3.4.
3.3.2 PCM slot assigner
The PCM slot assigner can connect each HFC-channel to an arbitrary PCM time slot. There-
fore, for a specified time slot
be written into the register A_SL_CFG[SLOT] as follows:
Typically, the data direction of a HFC-channel and its connected slot is the same. However,
for a direct connection between a PCM time slot and an E1 time slot, transmit and receive
direction have to be connected.
If two PCM time slots are connected to each other, incoming data on a PCM time slot is
transferred to the PCM slot assigner and stored in the PCM receive switching buffer of the
connected HFC-channel. From there it is read (i.e. same HFC-channel) and transmitted to a
transmit PCM time slot which is also connected to the HFC-channel.
3.3.3 E1 slot assigner
The E1 interface consists of 32 time slots for transmit data and 32 time slots for receive data.
In HFC-E1 applications these time slots are typically used for ISDN data transfer. Then
time slot 0 is reserved for the synchronization process and time slot 16 is normally used to
be the D-channel. All the other time slots are assigned to B-channels for the ISDN data
transmission.
Between the HFC-channels
with
for programming the E1 slot assigner.
slot array registers belong to this time slot. Please see Chapter 6 for details.
the inner circle of Figure 3.2.
100 of 272
4
5
A time slot is specified by writing its number and data direction into the register R_SLOT. Then all accesses to the
These channels have nothing to do with the mentioned D-channel and B-channels of the E1 interface, please refer to
Ò ¼ ¿½
A_SL_CFG : V_CH_DIR1[SLOT]
. There is no possibility to change this allocation, so there are no registers
: V_CH_NUM1[SLOT]
HFC-channel[
HFC-channel[
5
and the E1 time slots there is a simple assignment:
4
the connected HFC-channel number and data direction must
Data Sheet
Ò
Ò
Data flow
,RX] ° E1 slot[
,TX] ° E1 slot[
HFC-channel data direction
HFC-channel number
Ò
Ò
,TX]
,RX]
March 2003 (rev. A)
Cologne
Chip