HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 214

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Cologne
HFC-E1
BERT
Chip
10.1 BERT functionality
Bit Error Rate Test (BERT) is a very important test for communication lines. The bit er-
ror rate should be as low as possible. Increasing bit error rate is an early indication of a
malfunction of components or the communication wire link itself.
HFC-E1 includes a high performance pseudo random bit generator (PRBG) and a pseudo
random bit receiver with automatic synchronization capability. Error rate can be checked by
the also implemented Bit Error counter (BERT counter).
The PRBG can be set to a variety of different pseudo random bit patterns. With the bit
pattern V_PAT_SEQ in register R_BERT_WD_MD the transmit and receive detector can
be set to the trivial always ’0’ or always ’1’ pattern as well to well known patterns described
in ITU-T O.150 and O.151 specifications.
In every transmit HFC-channel the HDLC or transparent data is overwritten by bits from the
PRBG if V_BERT_EN in the register A_IRQ_MSK[FIFO] is set to ’1’. The random data
is only generated when the FIFO is processing data. So if subchannel processing is enabled
the PRBG is only enabled for less than 8 bits. Next PRGB bits are generated in the next
FIFO where a HFC-channel is processed and V_BERT_EN is set. The receive detector can
function properly only when the same receive FIFOs connected to the same E1 time slots are
enabled for BERT in receive direction as on the transmit FIFOs of the remote E1 interface
side.
The receive detector has an auto synchonization capability and also is enabled to automatic
detect an inverted BERT pattern. The auto synchronization only works with bit error rates
½¼
¾
¡
of less than
. If the error rate is higher synchronization will not be achieved. A
½
found synchronization is reported by V_BERT_SYNC
in register R_BERT_STA. If
the received pattern is inverted also V_BERT_INV_DATA is set.
A 16 bit BERT error count is available by reading the registers R_BERT_ECL and
R_BERT_ECH. The counter is reset when the R_BERT_ECL register is read.
To test a connection and the error detection of the BERT error counter on the receiver side of
an E1 link a BERT error can be generated. Setting the V_BERT_ERR generates one wrong
BERT bit in the outgoing data stream.
214 of 272
Data Sheet
March 2003 (rev. A)