HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 133

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

4.3 FIFO operation
4.3.1 HDLC transmit FIFOs
Data can be transmitted from the host bus interface to the FIFO with write access to the
registers A_FIFO_DATA0 and A_FIFO_DATA0_NOINC. The HFC-E1 converts the data
into HDLC code and tranfers it from the FIFO to the E1 or the PCM bus interface.
The HFC-E1 checks
HDLC flag (’01111110’) or continuous ’1’s (depending on the bit V_IFF of the register
A_CON_HDLC) and transmits it to the E1 interface. In this case
If also
counters remain unchanged. If the frame counters are unequal
HFC-E1 tries to transmit the next frame to the E1 interface. At the end of a frame (
reaches
there is another frame in the FIFO (
With every byte being written from the host bus side to the FIFO,
tomatically. If a complete frame has been sent into the FIFO
transmit the next frame. If the frame counter
change because
March 2003 (rev. A)
HFC-E1
F2
F1
½´ ¾µ
and
G
Without F0IO and C4IO clocks the HDLC controller does not work!
½
½
) it automatically generates the 16 bit CRC checksum and adds an ending flag. If
00h
02h
07h
1Fh
Important !
¾´ ¾µ
¾
½
only HDLC flags or continuous ’1’s are sent to the E1 interface and all
and
Z1
Z1
Z1
Z1
Z1
Z1
(see Fig. 4.1).
00
02
06
07
½
¾
and
FIFO handling and HDLC controller
Z1
Z1
are functions of
00
00
¾
Figure 4.1: FIFO organization
. If
Z2
Z2
½
00
02
Data Sheet
½
¾
) the
end of frame
end of frame
½
¾
½
and
(FIFO empty) the HFC-E1 generates a
is incremented the
¾
counter is incremented again.
¾
. Thus there are
SRAM
½
¾
must be incremented to
is incremented and the
¾
½
is not incremented.
-counters may also
is incremented au-
frame 02
frame 03
frame 06
frame 07
½´ ½µ
Cologne
Chip
,
133 of 272
OUTPUT
INPUT
¾´ ½µ
¾
,