HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 193

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

6.4.2 Read only register
March 2003 (rev. A)
HFC-E1
R_F0_CNTL
F0IO pulse counter, low byte
7..0
R_F0_CNTH
F0IO pulse counter, high byte
7..0
Bits
Bits
0x00
0
Value
Value
Reset
Reset
V_F0_CNTL
V_F0_CNTH
Name
Name
(read only)
(read only)
Data Sheet
PWM
Description
Low byte (bits 7 . . . 0) of the 125 s time counter
This register should be read first to ‘lock’ the value
of the R_F0_CNTH register until R_F0_CNTH
has also been read.
Description
High byte (bits 15 . . . 8) of the 125 s time
counter
The low byte must be read first (see register
R_F0_CNTL )
Cologne
Chip
193 of 272
0x18
0x19