HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 230

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
230 of 272
R_BRG_TIM2
Auxiliary bridge timing configuration register for timing 2
3..0
7..4
R_BRG_TIM3
Auxiliary bridge timing configuration register for timing 3
3..0
7..4
Bits
Bits
0
0
0
0
Reset
Value
Reset
Value
Name
V_BRG_TIM2_IDLE
V_BRG_TIM2_CLK
Name
V_BRG_TIM3_IDLE
V_BRG_TIM3_CLK
Auxiliary interface
(write only)
(write only)
Data Sheet
Idle cycles
Active cycles
Idle cycles
Active cycles
Description
Number of idle clock cycles for read / write signal
Number of active clock cycles for read / write signal
Description
Number of idle clock cycles for read / write signal
Number of active clock cycles for read / write signal
March 2003 (rev. A)
Cologne
Chip
0x4A
0x4B