HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 238

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
238 of 272
R_TI_WD
Timer and watchdog control register
3..0
7..4
Bits
0
0
Reset
Value
Name
V_EV_TS
V_WD_TS
Clock, reset, interrupt, timer and watchdog
(write only)
Data Sheet
Description
Timer event after ¾
0 = 250 s
1 = 500 s
2 = 1 ms
3 = 2 ms
4 = 4 ms
5 = 8 ms
6 = 16 ms
7 = 32 ms
8 = 64 ms
9 = 128 ms
0xA = 256 ms
0xB = 512 ms
0xC = 1.024 s
0xD = 2.048 s
0xE = 4.096 s
0xF = 8.192 s
Watchdog event after ¾
0 = 2 ms
1 = 4 ms
2 = 8 ms
3 = 16 ms
4 = 32 ms
5 = 64 ms
6 = 128 ms
7 = 256 ms
8 = 512 ms
9 = 1.024 s
0xA = 2.048 s
0xB = 4.096 s
0xC = 8.192 s
0xD = 16.384 s
0xE = 32.768 s
0xF = 65.536 s
Ò
¡ ¾ ¼ ×
Ò
¡ ¾ Ñ×
March 2003 (rev. A)
Cologne
Chip
0x1A