HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 110

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
FSM programming
The list index register R_FSM_IDX specifies the list index with bitmap V_IDX in the range
of
R_FIFO for list programming. So all array registers indexed with [FIFO] are indexed with
the V_IDX value instead.
The first FIFO of the list has to be specified in the register R_FIRST_FIFO with the di-
rection bit V_FIRST_FIFO_DIR and the FIFO number V_FIRST_FIFO_NUM. The next
FIFO has to be specified in the register A_FIFO_SEQ. Referring to Figure 3.9 the array
registers of the list entry
A FIFO handles more than one HFC-channel if this FIFO is entered several times in the ‘next
FIFO’ entries.
The connected HFC-channel and the FIFO configuration must be programmed in the same
way as in CSM. These settings belong to the FIFO which is specified in the previous list
entry under ‘next FIFO’ (or the R_FIRST_FIFO register for the first list entry).
110 of 272
is ‘FIFO q’.
¼
R_FSM_IDX
¿
. R_FSM_IDX has the same address as R_FIFO because in FSM it replaces
Index
R_FIFO_START
List
63
...
...
...
0
1
2
i
j
· ½
are assigned to FIFO
1st FIFO
FIFO m
FIFO n
FIFO q
FIFO
Figure 3.9: FSM list processing
...
Data Sheet
Channel
Data flow
channel a
channel b
channel c
channel d
channel e
List Entries:
configuration
configuration
configuration
configuration
configuration
Register
settings
Õ
because ‘next FIFO’ entry at list index
...
...
end of list
1st FIFO
FIFO m
FIFO n
FIFO o
FIFO q
FIFO
Next
A_CON_HDLC [i]
March 2003 (rev. A)
A_BYTE_PAR [i]
A_FIFO_SEQ [i]
A_CHANNEL [i]
A_IRQ_MSK [i]
Cologne
Chip