HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 130

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
There are up to 32 receive FIFOs and up to 32 transmit FIFOs with 64 HDLC controllers in
whole. The HDLC circuits are located on the E1 interface side of the FIFOs. Thus plain data
is always stored in the FIFOs. Automatic zero insertion is done in HDLC mode when HDLC
data goes from the FIFOs to the E1 interface or to the PCM bus (transmit FIFO operation).
Automatic zero deletion is done in HDLC mode when the HDLC data comes from the E1
interface or PCM bus (receive FIFO operation).
There is a transmit and a receive FIFO for each E1 time slot (even for time slot 0).
The FIFO control registers are used to select and control the FIFOs of the HFC-E1. The
FIFO register set exists for every FIFO number and receive / transmit direction. The FIFO is
selected by the FIFO select register R_FIFO.
All FIFOs are disabled after reset (hardware reset, soft reset or HFC reset). With the register
A_CON_HDLC the selected FIFO is enabled by setting at least one of V_HDLC_TRP or
V_TRP_IRQ to a value different from zero.
4.1 FIFO counters
The FIFOs are realized as ring buffers in the internal or external SRAM. They are controlled
by counters. The counter sizes depend on the setting of the FIFO sizes.
counter and
Each counter points to a byte position in the SRAM. On a FIFO input operation
mented. On an output operation
After every pulse on the F0IO signal HDLC bytes are written into the E1 interface (from a
transmit FIFO) and HDLC bytes are read from the E1 interface (to a receive FIFO).
Additionally there are two counters
frames. Their width is 4 bit for 32 kByte SRAM and 5 bit for larger SRAMs. They form a
ring buffer as
incremented when a complete frame has been read from the FIFO. If
complete frame in the FIFO.
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½
is incremented when a complete frame has been received and stored in the FIFO.
¾
½
is the FIFO output counter.
and
¾
Table 4.2:
do, too.
FIFO handling and HDLC controller
RAM size
¾
-counter range with different RAM sizes
128k x 8
512k x 8
32k x 8
is incremented. If
½
Data Sheet
and
0x00
0x00
0x00
ÅÁÆ
¾
for every FIFO for counting the HDLC
0x0F
0x1F
0x1F
Å
½
¾
the FIFO is empty.
March 2003 (rev. A)
½
½
is the FIFO input
¾
Cologne
Chip
there is no
½
is incre-
¾
is