HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 191

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_SH0L
CODEC enable signal SHAPE0, low byte
This multi-register is selected with bitmap V_PCM_ADDR = 0xC of the regis-
ter R_PCM_MD0.
7..0
R_SH0H
CODEC enable signal SHAPE0, high byte
This multi-register is selected with bitmap V_PCM_ADDR = 0xD of the regis-
ter R_PCM_MD0.
7..0
R_SH1L
CODEC enable signal SHAPE1, low byte
This multi-register is selected with bitmap V_PCM_ADDR = 0xE of the regis-
ter R_PCM_MD0.
7..0
Bits
Bits
Bits
0
0
0
Value
Value
Value
Reset
Reset
Reset
V_SH0L
V_SH0H
V_SH1L
Name
Name
Name
PCM interface
(write only)
(write only)
(write only)
Data Sheet
Description
Shape bits 7 . . . 0
Every bit is used for 1/2 C4IO clock cycle.
Description
Shape bits 15 . . . 8
Every bit is used for 1/2 C4IO clock cycle.
Bit 7 of V_SH0H defines the value for the rest of
the period.
Description
Shape bits 7 . . . 0
Every bit is used for 1/2 C4IO clock cycle.
Cologne
Chip
191 of 272
0x15
0x15
0x15