HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 185

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_SL_SEL1
Slot selection register for pin F1_1
This multi-register is selected with bitmap V_PCM_ADDR = 1 of the register
R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_1 is disabled.
6..0
7
Bits
G
For selecting slot 0 the value that has to be written to
the
R_SL_SEL0 . . . R_SL_SEL7 depends on the PCM data rate:
Please note that time slot 0 for PCM128 can only be used with
V_SH_SEL0 . . . V_SH_SEL7 = 0 (SHAPE 0) in the registers
R_SL_SEL0 . . . R_SL_SEL7.
0x7F
1
Value
Reset
Important !
bitmap
V_SL_SEL1
Name
V_SH_SEL1
V_SL_SEL0
PCM data rate Value
PCM30
PCM64
PCM128
PCM interface
(write only)
Data Sheet
. . . V_SL_SEL7
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 ·½ for
F1_1. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
0x1F
0x3F
0x7F
of
the
register
Cologne
Chip
185 of 272
0x15