HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 197

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

7.3 Register description
7.3.1 Write only register
March 2003 (rev. A)
HFC-E1
R_PWM0
Modulator register for pin PWM0
7..0
R_PWM1
Modulator register for pin PWM1
7..0
Bits
Bits
0
0
Value
Value
Reset
Reset
V_PWM0
V_PWM1
Name
Name
(write only)
(write only)
Data Sheet
PWM
Description
PWM duty cycle
The value specifies the number of clock periods
where the output signal of PWM0 is high during a
256 clock periods cycle, e.g.
0x00 = no pulse, always low
0x80 = ½ ½ duty cycle
0xFF = 1 clock period low after 255 clock periods
high
Description
PWM duty cycle
The value specifies the number of clock periods
where the output signal of PWM1 is high during a
256 clock periods cycle, e.g.
0x00 = no pulse, always low
0x80 = ½ ½ duty cycle
0xFF = 1 clock period low after 255 clock periods
high
Cologne
Chip
197 of 272
0x38
0x39