HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 164

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
164 of 272
R_TX_FR2
E1 time slot 0 configuration, register 2
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
Reset
Value
Name
V_TX_MF
V_TRP_SL0
V_TX_SL0_RAM
(reserved)
V_TX_E
V_NEG_E
V_XS13_ON
V_XS15_ON
(write only)
E1 interface
Data Sheet
Description
framing selection
’0’ = doubleframe format
’1’ = multiframe mode (CRC4)
Time slot 0 transparent mode
’0’ = normal operation
’1’ = the HFC-channel 0 data or RAM data will be
used and the registers R_TX_FR0 and
R_TX_FR1 are ignored
Time slot 0 data source
’0’ = time slot 0 data comes from HFC-channel 0
’1’ = time slot 0 data comes from alternating RAM
buffer
Must be ’0’.
Automatic transmission of submultiframe status
’0’ = XS13 and XS15 bits from V_XS13_ON and
V_XS15_ON of this register are transmitted
’1’ = E-bits are transmitted (CRC calculation result)
Polarity of E-bits
’0’ = positive E-bits
’1’ = negative E-bits
Transmit spare bit XS13
(Frame 13 of multiframe)
’0’ = XS13 is ’0’
’1’ = XS13 is ’1’
Note: This bit is only valid in CRC multiframe.
Transmit spare bit XS15
(Frame 15 of multiframe)
’0’ = XS15 is ’0’
’1’ = XS15 is ’1’
Note: This bit is only valid in CRC multiframe.
March 2003 (rev. A)
Cologne
Chip
0x2E