HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 161

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_TX1
E1 transmitter configuration, register 1
0
1
2
4..3
5
6
7
Bits
0
0
0
0
0
0
Value
Reset
(reserved)
Name
V_INV_CLK
V_EXCHG_DATA_LI
V_AIS_OUT
V_ATX
V_NTRI
V_AUTO_ERR_RES
(write only)
E1 interface
Data Sheet
Description
Polarity of mark
’0’ = normal operation
’1’ = inverted clock
This bit is only valid with CMI code.
TxD-exchange
’0’ = normal operation
’1’ = exchange data output lines R_A and R_B
Generate AIS output signal
Continuous ’1’s are generated.
Must be ’00’.
Transmitter mode
’0’ = standard transmitter
’1’ = analog transmitter tandem mode
No tristate
’0’ = tristate for gap between pulses enabled
’1’ = tristate for gap between pulses disabled
Error counter mode
’0’ = normal counter operation after reaching
maximum count, counter starts at 0 again
’1’ = every second the error counters will be reset
automatically after they are latched
Note: The latched state should be read within the
next second. During updating reading should be
avoided.
Cologne
Chip
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