HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 54

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
2.3 ISA Plug and Play interface
ISA Plug and Play mode is selected by MODE0
eight consecutive addresses in the I/O map of a PC for operation. Usually also one out of
several ISA IRQ lines is used. Section 2.3.1 describes how to configure the interrupt lines of
the HFC-E1.
The port address is selected by the lines SA0 . . . SA15. The address with SA2
for register selection via the CIP (Control Internal Pointer) and the address with SA2
is used for data read / write like shown in Table 2.10. The bits SA3 . . . SA15 are decoded by
the address decoder to match the PnP configuration address.
The HFC-E1 has no memory or DMA access to any component on the ISA PC bus. Because
of its characteristic power drive no external driver for the ISA PC bus data lines is needed.
54 of 272
203 . . . 206,1 . . . 4
Table 2.10: ISA address decoding (X
106 . . . 112
Table 2.9: Overview of the ISA PnP interface pins
Number
31 . . . 39
43 . . . 51
SA2
8 . . . 17
X
X
0
0
1
1
Universal external bus interface
198
18
20
21
22
25
30
/IOR
X
1
0
1
0
1
Name
SA15 . . . SA8
SA7 . . . SA0
SD15 . . . SD8
SD7 . . . SD0
/IOIS16
/AEN
/IOR
/IOW
/BUSDIR
/SBHE
RESET
IRQ6 . . . IRQ0
Data Sheet
/IOW
X
1
1
0
1
0
/AEN
X
Description
Address byte 1
Address byte 0
Data byte 1
Data byte 0
ISA Interrupt Request 6 . . . 0
16 bit access enable
Address Enable
Read Enable
Write Enable
Bus Direction
High byte enable
Reset high active
1
0
0
0
0
¼
and MODE1
read data
write data
read CIP
write CIP
Operation
no access
no access
don’t care)
½
. The HFC-E1 needs
March 2003 (rev. A)
Cologne
Chip
’1’ is used
’0’