HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 96

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
3.2 Flow controller
The various connections between FIFOs, E1 time slots and PCM time slots are set up by
programming the flow controller, the channel assigner and the PCM slot assigner.
The flow controller sets up connections between FIFOs and the E1 interface, FIFOs and the
PCM interface and between the E1 and PCM interface. The bitmap V_DATA_FLOW of the
register A_CON_HDLC (which exists for each FIFO) configures these connections. The
numbering of transmit and corresponding receive FIFOs, HFC-channels and PCM time slots
is independent from each other. But in practice the connection table is more clear if the same
number is chosen for corresponding transmit and receive direction.
A direct connection between two PCM time slots can be set up inside the PCM slot assigner
and will be described in Section 3.3.
The flow controller operates on HFC-channel data. Nevertheless it is programmed with
a bitmap of a FIFO-indexed array register. With this concept it is possible to change the
FIFO-to-HFC-channel assignment of a ready-configured FIFO without re-programming its
parameters again.
The internal structure of the flow controller contains
Switching buffers
The switching buffers decouple the data inside the flow controller from the data that is trans-
mitted / received from / to the E1 and PCM interfaces. With every 125 s cycle the switching
buffers change their pointers.
If a byte is read from the FIFO and written into a switching buffer, it is transmitted by the
connected interface during the next 125 s cycle. In the reverse case, a received byte which
is stored in a switching buffer is copied to the FIFO during the next 125 s cycle.
A direct PCM-to-E1 connection delays each data byte two cycles. That means the received
byte is stored in the switching buffer during the first 125 s cycle, then copied into the trans-
mit buffer during the second 125 s cycle and finally transmitted from the interface during
the third 125 s cycle. If the conference unit is switched on, there is an additional 125 s
delay, because the summation of the whole frame is processed in the memory (see Section 8).
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4 switching buffers, i.e. one for the E1 and PCM interface in transmit and receive
direction each and
3 switches to control the data paths.
Data Sheet
Data flow
March 2003 (rev. A)
Cologne
Chip