XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet
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XC2VP20-6FF1152C
Manufacturer Part Number
XC2VP20-6FF1152C
Description
Pro Platform FPGA
Manufacturer
Xilinx, Inc.
Datasheet
1.XC2VP20-6FF1152C.pdf
(268 pages)
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Company:
Part Number:
XC2VP20-6FF1152C
Manufacturer:
XILINX
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DS083-1 (v1.0) January 31, 2002
Summary of Virtex-II Pro Features
•
•
The members and resources of the Virtex-II Pro family are
shown in
Rocket I/O Features
•
•
•
•
•
Table 1: Virtex-II Pro FPGA Family Members
DS083-1 (v1.0) January 31, 2002
Advance Product Specification
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP50
Device
High-performance Platform FPGA solution including
-
-
Based on Virtex™-II Platform FPGA technology
-
-
-
-
-
-
-
-
Full-duplex serial transceiver (SERDES) capable of
baud rates from 622 Mb/s to 3.125 Gb/s
80 Gb/s duplex data rate (16 channels)
Monolithic clock synthesis and clock recovery (CDR)
Fibre Channel, Gigabit Ethernet, 10 Gb Attachment
Unit Interface (XAUI), and Infiniband-compliant
transceivers
8-, 16-, or 32-bit selectable internal FPGA interface
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Up to sixteen Rocket I/O™ embedded multi-gigabit
transceiver blocks (based on Mindspeed's
SkyRail™ technology)
Up to four IBM
Flexible logic resources
SRAM-based in-system configuration
Active Interconnect™ technology
SelectRAM™ memory hierarchy
Dedicated 18-bit x 18-bit multiplier blocks
High-performance clock management circuitry
SelectI/O™-Ultra technology
Digitally Controlled Impedance (DCI) I/O
Table
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Transceiver
Rocket I/O
Blocks
1.
16
4
4
8
8
®
PowerPC
Processor
PowerPC
Blocks
R
0
1
1
2
4
®
RISC processor blocks
Row x Col
(1 CLB = 4 slices = Max 128 bits)
16 x 22
40 x 22
40 x 34
56 x 46
88 x 70
Array
22,592
Slices
1,408
3,008
4,928
9,280
CLB
0
0
www.xilinx.com
1-800-255-7778
0
Distributed
Maximum
RAM (Kb)
154
290
706
44
94
Virtex-II Pro™ Platform FPGAs:
Introduction and Overview
Advance Product Specification
•
•
•
•
•
•
•
•
•
PowerPC RISC Core Features
•
•
•
•
•
•
•
•
•
•
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8B /10B encoder and decoder
50 /75 on-chip selectable transmit and receive
terminations
Programmable comma detection
Channel bonding support (two to sixteen channels)
Rate matching via insertion/deletion characters
Four levels of selectable pre-emphasis
Five levels of output differential voltage
Per-channel internal loopback modes
2.5V transceiver supply voltage
Embedded 300+ MHz Harvard architecture core
Low power consumption: 0.9 mW/MHz
Five-stage data path pipeline
Hardware multiply/divide unit
Thirty-two 32-bit general purpose registers
16 KB two-way set-associative instruction cache
16 KB two-way set-associative data cache
Memory Management Unit (MMU)
-
-
Dedicated on-chip memory (OCM) interface
Supports IBM CoreConnect™ bus architecture
Debug and trace support
Timer facilities
64-entry unified Translation Look-aside Buffers
(TLB)
Variable page sizes (1 KB to 16 MB)
18 X 18 Bit
Multiplier
Blocks
216
12
28
44
88
Blocks
18 Kb
Block SelectRAM
216
12
28
44
88
Block RAM
1,584
3,888
Max
(Kb)
216
504
792
DCMs
4
4
4
8
8
I/O Pads
Max
204
348
396
564
852
1
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