XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 35
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XC2VP20-6FF1152C
Manufacturer Part Number
XC2VP20-6FF1152C
Description
Pro Platform FPGA
Manufacturer
Xilinx, Inc.
Datasheet
1.XC2VP20-6FF1152C.pdf
(268 pages)
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Multiplexers
Virtex-II Pro function generators and associated multiplex-
ers can implement the following:
•
•
•
•
Fast Lookahead Carry Logic
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II Pro CLB has two separate carry
chains, as shown in the
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
4:1 multiplexer in one slice
8:1 multiplexer in two slices
16:1 multiplexer in one CLB element (4 slices)
32:1 multiplexer in two CLB elements (8 slices)
R
G
G
F
F
Figure
30.
Slice S3
Slice S2
Figure 29: MUXF5 and MUXFX multiplexers
Slice S1
Slice S0
www.xilinx.com
1-800-255-7778
G
G
F
F
Each Virtex-II Pro slice has one MUXF5 multiplexer and
one MUXFX multiplexer. The MUXFX multiplexer imple-
ments the MUXF6, MUXF7, or MUXF8, as shown in
Figure
one MUXF7 multiplexer and one MUXF8 multiplexer. Exam-
ples of multiplexers are shown in the Virtex-II Pro User
Guide. Any LUT can implement a 2:1 multiplexer.
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II Pro device is running upward. The ded-
icated carry path and carry multiplexer (MUXCY) can also
be used to cascade function generators for implementing
wide logic functions.
Virtex-II Pro™ Platform FPGAs: Functional Description
CLB
29. Each CLB element has two MUXF6 multiplexers,
MUXF8 combines
the two MUXF7 outputs
(Two CLBs)
MUXF6 combines the two MUXF5
outputs from slices S2 and S3
MUXF7 combines the two MUXF6
outputs from slices S0 and S2
MUXF6 combines the two MUXF6
outputs from slices S0 and S1
DS031_08_110200
35
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