XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 13

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Receiver
Deserializer
The Rocket I/O transceiver core accepts serial differential
data on its RXP and RXN inputs. The clock/data recovery
circuit extracts the clock and retimes incoming data to this
clock. It uses a fully monolithic PLL requiring no external
components. The clock/data recovery circuitry extracts both
phase and frequency from the incoming data stream. The
recovered clock is presented on output RXRECCLK at 1/20
of the received serial data rate.
The receiver is capable of handling either transition-rich
8B/10B streams or scrambled streams, and can withstand a
string of up to 75 non-transitioning bits without an error.
Word alignment is dependent on the state of comma detect
bits. If comma detect is enabled, the transceiver will recog-
nize up to two 10-bit preprogrammed characters. Upon
detection of the character or characters, the comma detect
output is driven high and the data is synchronously aligned.
If a comma is detected and the data is aligned, no further
alignment alteration will take place. If a comma is received
and realignment is necessary, the data is realigned and an
indication is given at the receiver interface. The realignment
indicator is a distinct output. The transceiver will continu-
ously monitor the data for the presence of the 10-bit charac-
ter(s). Upon each occurrence of the 10-bit character, the
data is checked for word alignment. If comma detect is dis-
abled, the data will not be aligned to any particular pattern.
The programmable option allows a user to align data on
comma+, comma–, both, or a unique user-defined and pro-
grammed sequence.
The receiver can be configured to reverse the RXP and
RXN inputs. This can be useful in the event that printed cir-
cuit board traces have been reversed.
Receiver Termination
On-chip termination is provided at the receiver, eliminating
the need for external termination. The receiver includes pro-
grammable on-chip termination circuitry for 50 (default) or
75
8B/10B Decoder
An optional 8B/10B decoder is included. A programmable
option allows the decoder to be bypassed. When the
8B/10B decoder is bypassed, the 10-bit character order is,
for example,
The decoder uses the same table that is used for Gigabit
Ethernet, Fibre Channel, and InfiniBand. In addition to
decoding all data and K-characters, the decoder has sev-
eral extra features. The decoder separately detects both
“disparity errors” and “out-of-band” errors. A disparity error
is the reception of 10-bit character that exists within the
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
RXCHARISK[0]
RXRUNDISP[0]
RXDATA[7:0]
impedance.
R
(last bit received is RXDATA[0])
(first bit received)
www.xilinx.com
1-800-255-7778
8B/10B table but has an incorrect disparity. An out-of-band
error is the reception of a 10-bit character that does not exist
within the 8B/10B table. It is possible to obtain an
out-of-band error without having a disparity error. The
proper disparity is always computed for both legal and ille-
gal characters. The current running disparity is available at
the RXRUNDISP signal.
The 8B/10B decoder performs a unique operation if
out-of-band data is detected. If out-of-band data is
detected, the decoder signals the error and passes the ille-
gal 10-bits through and places them on the outputs. This
can be used for debugging purposes if desired.
The decoder also signals the reception of one of the 12 valid
K-characters. In addition, a programmable comma detect is
included. The comma detect signal registers a comma on
the receipt of any comma+, comma–, or both. Since the
comma is defined as a 7-bit character, this includes several
out-of-band characters. Another option allows the decoder
to detect only the three defined commas (K28.1, K28.5, and
K28.7) as comma+, comma–, or both. In total, there are six
possible options, three for valid commas and three for "any
comma."
It should be noted that all bytes (1, 2, or 4) at the RX FPGA
interface will each have their own individual 8B/10B indica-
tors (K-character, disparity error, out-of-band error, current
running disparity, and comma detect).
Loopback
In order to facilitate testing without having the need to either
apply patterns or measure data at GHz rates, two program-
mable loop-back features are available.
One option, serial loopback, places the gigabit transceiver
into a state where transmit data is directly fed back to the
receiver. An important point to note is that the feedback path
is at the output pads of the transmitter. This tests the
entirety of the transmitter and receiver.
The second loopback path is a parallel path that checks the
digital circuitry. When the parallel option is enabled, the
serial loopback path is disabled. However, the transmitter
outputs remain active and data is transmitted over a link. If
TXINHIBIT is asserted, TXP is forced to 0 until TXINHIBIT
is de-asserted.
Elastic and Transmitter Buffers
Both the transmitter and the receiver include buffers
(FIFOs) in the datapath. This section gives the reasons for
including the buffers and outlines their operation.
Receiver Buffer
The receiver buffer is required for two reasons:
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Virtex-II Pro™ Platform FPGAs: Functional Description
Clock corection to accommodate the slight difference in
frequency between the recovered clock RXRECCLK
and the internal FPGA user clock RXUSRCLK
Channel bonding to allow realignment of the input
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