XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 84

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Pin-to-Pin Output Parameter Guidelines
Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
Without DCM
Table 41: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
Without DCM
84
Notes:
1.
2.
3.
LVCMOS25 Global Clock Input to Output
Delay using Output Flip-flop, 12 mA,
Fast Slew Rate, without DCM.
For data output with different standards,
adjust the delays with the values shown
in
Characteristics Standard
Adjustments, page
Global Clock and OFF without DCM
IOB Output Switching
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
Table
DCM output jitter is already included in the timing calculation.
30.
Description
73.
CC
threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Symbol
T
ICKOF
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XC2VP20
XC2VP50
XC2VP2
XC2VP4
XC2VP7
Device
–8
Speed Grade
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
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7
–
6
Units
ns
ns
ns
ns
ns
R