XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 72

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Switching Characteristics
Table 27: IOB Input Switching Characteristics Standard Adjustments (Continued)
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVCMOS25 with 12 mA drive and fast slew rate. For other standards,
adjust the delays with the values shown in
Table 28: IOB Output Switching Characteristics
72
Notes:
1.
Propagation Delays
3-State Delays
Sequential Delays
Standard-specific data input delay
adjustments (continued)
O input to Pad
O input to Pad via transparent latch
T input to Pad high-impedance
T input to valid data on Pad
T input to Pad high-impedance via
transparent latch
T input to valid data on Pad via transparent latch
GTS to Pad high-impedance
Clock CLK to Pad
Clock CLK to Pad high-impedance
(synchronous)
Clock CLK to valid data on Pad
(synchronous)
Input timing for LVTTL is measured at 1.4V. For other I/O standards, see
Description
(2)
Description
(2)
(2)
(2)
T
T
T
T
IOB Output Switching Characteristics Standard Adjustments, page
IHSTL_IV_DCI_18
T
T
T
IHSTL_III_DCI_18
T
T
T
IHSTL_II_DCI_18
T
IHSTL_I_DCI_18
ISSTL2_II_DCI
ISSTL3_II_DCI
T
IHSTL_III_DCI
IHSTL_IV_DCI
ISSTL2_I_DCI
ISSTL3_I_DCI
IHSTL_II_DCI
T
Symbol
IULVDS_25
ILDT_25
www.xilinx.com
1-800-255-7778
T
T
T
Symbol
T
T
T
T
T
IOTLPON
IOTLPHZ
T
IOCKON
IOCKHZ
T
IOOLP
IOTON
IOCKP
IOTHZ
IOOP
HSTL_IV_DCI_18
HSTL_III_DCI_18
GTS
HSTL_II_DCI_18
HSTL_I_DCI_18
HSTL_IV_DCI
SSTL2_II_DCI
SSTL3_II_DCI
HSTL_III_DCI
SSTL2_I_DCI
SSTL3_I_DCI
HSTL_II_DCI
ULVDS_25
Standard
LDT_25
Table
30.
–8
Speed Grade
–8
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
Speed Grade
–
7
–
7
–
6
–
6
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
Units
73.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R