XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 40

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
Table 16: Dual-Port Mode Configurations
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kb block is accessible
from port A or B. If both ports are configured in either 16K x
1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the 16 K-bit
block is accessible from Port A or Port B. All other configu-
rations result in one port having access to an 18 Kb memory
block and the other port having access to a 16 K-bit subset
of the memory block equal to 16 Kbs.
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in
inputs and outputs and are independently clocked.
Port Aspect Ratios
Table 17
18 Kb block SelectRAM. Virtex-II Pro block SelectRAM also
40
Figure 36: 18 Kb Block SelectRAM in Dual-Port Mode
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
shows the depth and the width aspect ratios for the
Figure
DIB
DIPA
ADDRA
WEA
ENA
SSRA
DIPB
ADDRB
WEB
ENB
SSRB
DIA
512 x 36
512 x 36
CLKA
CLKB
16K x 1
16K x 1
1K x 18
1K x 18
18-Kbit Block SelectRAM
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
36. The two ports have independent
512 x 36
DOPA
DOPB
16K x 1
1K x 18
1K x 18
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
DOA
DOB
DS031_11_102000
www.xilinx.com
1-800-255-7778
512 x 36
16K x 1
1K x 18
4K x 4
8K x 2
2K x 9
4K x 4
2K x 9
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
Table 17: 18 Kb Block SelectRAM Port Aspect Ratio
Read/Write Operations
The Virtex-II Pro block SelectRAM read operation is fully
synchronous. An address is presented, and the read opera-
tion is enabled by control signal ENA or ENB. Then,
depending on clock polarity, a rising or falling clock edge
causes the stored data to be loaded into output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA and WEB in addition to ENA or
ENB. Then, again depending on the clock input mode, a ris-
ing or falling clock edge causes the data to be loaded into
the memory cell addressed.
A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1. WRITE_FIRST
Width
18
36
1
2
4
9
The WRITE_FIRST option is a transparent mode. The
same clock edge that writes the data input (DI) into the
512 x 36
16,384
Depth
16K x 1
1K x 18
8,192
4,096
2,048
1,024
2K x 9
8K x 2
4K x 4
512
Address Bus
ADDR[13:0]
ADDR[12:0]
ADDR[11:0]
ADDR[10:0]
ADDR[9:0]
ADDR[8:0]
512 x 36
16K x 1
1K x 18
DS083-2 (v1.0) January 31, 2002
8K x 2
Advance Product Specification
DATA[15:0]
DATA[31:0]
Data Bus
DATA[1:0]
DATA[3:0]
DATA[7:0]
DATA[0]
512 x 36
16K x 1
Parity Bus
Parity[1:0]
Parity[3:0]
Parity[0]
N/A
N/A
N/A
R