XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 50

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
ured, the data for the next device is routed internally to the
DOUT pin. The data on the DOUT pin changes on the rising
edge of CCLK.
Slave-serial mode is selected by applying [111] to the mode
pins (M2, M1, M0). A weak pull-up on the mode pins makes
slave serial the default mode if the pins are left uncon-
nected.
Master-Serial Mode
In master-serial mode, the CCLK pin is an output pin. It is the
Virtex-II Pro FPGA device that drives the configuration clock
on the CCLK pin to a Xilinx Serial PROM which in turn feeds
bit-serial data to the DIN input. The FPGA accepts this data
on each rising CCLK edge. After the FPGA has been loaded,
the data for the next device in a daisy-chain is presented on
the DOUT pin after the rising CCLK edge.
The interface is identical to slave serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration.
Slave SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the Virtex-II Pro FPGA device
with a BUSY flag controlling the flow of data. An external
data source provides a byte stream, CCLK, an active Low
Chip Select (CS_B) signal and a Write signal (RDWR_B). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low. Data can also be read using the
SelectMAP mode. If RDWR_B is asserted, configuration
data is read out of the FPGA as part of a readback opera-
tion.
Table 26: Virtex-II Pro Configuration Mode Pin Settings
50
Notes:
1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls
2. Daisy chaining is possible only in modes where Serial D
Master Serial
Slave Serial
Master SelectMAP
Slave SelectMAP
Boundary Scan
whether or not the pullups are used.
support daisy chaining of downstream devices.
Configuration Mode
(1)
M2
0
1
0
1
1
M1
0
1
1
1
0
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1-800-255-7778
OUT
is used. For example, in SelectMAP modes, the first device does NOT
M0
0
1
1
0
1
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback using the per-
sist option.
Multiple Virtex-II Pro FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, RDWR_B, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
deasserting the CS_B pin of each device in turn and writing
the appropriate data.
Master SelectMAP Mode
This mode is a master version of the SelectMAP mode. The
device is configured byte-wide on a CCLK supplied by the
Virtex-II Pro FPGA device. Timing is similar to the Slave
SerialMAP mode except that CCLK is supplied by the
Virtex-II Pro FPGA.
Boundary-Scan (JTAG, IEEE 1532) Mode
In boundary-scan mode, dedicated pins are used for config-
uring the Virtex-II Pro device. The configuration is done
entirely through the IEEE 1149.1 Test Access Port (TAP).
Virtex-II Pro device configuration using Boundary scan is
compliant with IEEE 1149.1-1993 standard and the new
IEEE 1532 standard for In-System Configurable (ISC)
devices. The IEEE 1532 standard is backward compliant
with the IEEE 1149.1-1993 TAP and state machine. The
IEEE Standard 1532 for In-System Configurable (ISC)
devices is intended to be programmed, reprogrammed, or
tested on the board via a physical and logical protocol. Con-
figuration through the boundary-scan port is always avail-
able, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes.
CCLK Direction
Out
Out
N/A
In
In
Data Width
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
1
1
8
8
1
Serial D
Yes
Yes
No
No
No
OUT
(2)
R