XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 88

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

DCM Timing Parameters
Input Clock Tolerances
Table 45: Input Clock Tolerances
88
Notes:
1.
2.
3.
Input Clock Low/high Pulse Width
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
Input Clock Period Jitter (Low Frequency Mode)
Input Clock Period Jitter (High Frequency Mode)
Feedback Clock Path Delay Variation
PSCLK
CLKIN
CLKIN (using DLL outputs) (1)
CLKIN (using CLKFX outputs) (2)
CLKIN (using DLL outputs) (1)
CLKIN (using CLKFX outputs) (2)
CLKIN (using DLL outputs) (1)
CLKIN (using CLKFX outputs) (2)
CLKIN (using DLL outputs) (1)
CLKIN (using CLKFX outputs) (2)
CLKFB off-chip feedback
“DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
If both DLL and CLKFX outputs are used, follow the more restrictive specification.
Specification also applies to PSCLK.
(3)
Description
PSCLK_PULSE
CLKIN_PULSE
CLKIN_CYC_JITT_DLL_HF
CLKIN_CYC_JITT_DLL_LF
CLKIN_PER_JITT_DLL_HF
CLKIN_PER_JITT_DLL_LF
CLKFB_DELAY_VAR_EXT
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX_HF
CLKIN_CYC_JITT_FX_LF
CLKIN_PER_JITT_FX_LF
Symbol
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< 1MHz
1 - 10 MHz
10 - 25 MHz
25 - 50 MHz
50 - 100 MHz
100 - 150 MHz
150 - 200 MHz
200 - 250 MHz
250 - 300 MHz
300 - 350 MHz
350 - 400 MHz
> 400 MHz
Constraints
Min
–8
Max
Speed Grade
Min
–7
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
Max
Min
–6
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ns
R