XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 27

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Within a bank, output standards can be mixed only if they
use the same V
Table
their open-drain outputs do not depend on V
Some input standards require a user-supplied threshold
voltage, V
matically configured as inputs for the V
imately one in six of the I/O pins in the bank assume this
role.
V
consequently only one V
each bank. However, for correct operation, all V
the bank must be connected to the external reference volt-
age source.
The V
device pinout tables. Within a given package, the number of
V
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
REF
REF
Figure 15: Virtex-II Pro I/O Banks: Top View for
Figure 16: Virtex-II Pro I/O Banks: Top View for
7. GTL and GTLP appear under all voltages because
pins within a bank are interconnected internally, and
CCO
and V
REF
and the V
R
Flip-Chip Packages (FF and BF)
CCO
. In this case, certain user-I/O pins are auto-
CCO
pins can vary depending on the size of
Wire-Bond Packages
(CS, FG, and BG)
. Compatible standards are shown in
Bank 1
REF
Bank 4
Bank 0
Bank 5
pins for each bank appear in the
REF
voltage can be used within
Bank 0
Bank 5
Bank 1
Bank 4
ug002_c2_014_112900
REF
ds031_66_112900
voltage. Approx-
CCO
REF
.
pins in
www.xilinx.com
1-800-255-7778
device. In larger devices, more I/O pins convert to V
pins. Since these are always a superset of the V
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
Table 7: Compatible Output Standards
All V
nected to the V
devices, some V
nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
connected to the V
larger device.
Digitally Controlled Impedance (DCI)
Today’s chip output signals with fast edge rates require ter-
mination to prevent reflections and maintain signal integrity.
High pin count packages (especially ball grid arrays) can
not accommodate external termination resistors.
Virtex-II Pro DCI provides controlled impedance drivers and
on-chip termination for single-ended I/Os. This eliminates
the need for external resistors, and improves signal integrity.
The DCI feature can be used on any IOB by selecting one of
the DCI I/O standards.
When applied to inputs, DCI provides input parallel termina-
tion. When applied to outputs, DCI provides controlled
impedance drivers (series termination) or output parallel
termination.
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external refer-
ence resistors must be connected to two dual-function pins
Virtex-II Pro™ Platform FPGAs: Functional Description
Notes:
1. LVPECL, LVDS_33, LVDSEXT_33, and AGP-2X are not
2. Perfect impedance matching is required for 3.3V standards.
3. For optimum performance, it is recommended that PCI be
3.3V
V
2.5V
1.8V
1.5V
1.2V
CCO
supported.
used in conjunction with LVDCI_33. Contact Xilinx for more
details.
REF
(2)
pins for the largest device anticipated must be con-
PCI
LVDCI_33, SSTL3_DCI (I & II)
SSTL2 (I & II), LVCMOS25, GTL, GTLP,
LVDS_25, LVDSEXT_25, LVDCI_25,
LVDCI_DV2_25, SSTL2_DCI (I & II), LDT,
ULVDS, BLVDS
HSTL (I, II, III, & IV), HSTL_DCI (I,II, III & IV),
LVCMOS18, GTL, GTLP, LVDCI_18,
LVDCI_DV2_18
HSTL (I, II, III, & IV), HSTL_DCI (I,II, III & IV),
LVCMOS15, GTL, GTLP, LVDCI_15,
LVDCI_DV2_15, GTLP_DCI
GTL_DCI
REF
(3)
CCO
, LVTTL, SSTL3 (I & II), LVCMOS33,
voltage and not used for I/O. In smaller
CCO
pins used in larger devices do not con-
Compatible Standards
voltage to permit migration to a
(1)
(1)
REF
pins
REF
27