XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 2

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

General Description
Virtex-II Pro Platform FPGA Technology
•
•
•
•
•
•
1. PCI supported in some banks only.
2
SelectRAM memory hierarchy
-
-
-
Arithmetic functions
-
-
Flexible logic resources
-
-
-
-
-
High-performance clock management circuitry
-
-
Active Interconnect technology
-
-
-
SelectI/O-Ultra technology
-
-
-
-
-
-
-
Up to 4 Mb of True Dual-Port RAM in 18 Kb block
SelectRAM resources
Up to 706 Kb of distributed SelectRAM resources
High-performance interfaces to external memory
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
Up to 45,184 internal registers/latches with Clock
Enable
Up to 45,184 look-up tables (LUTs) or cascadable
variable (1 to 16 bits) shift registers
Wide multiplexers and wide-input function support
Horizontal cascade chain and Sum-of-Products
support
Internal 3-state busing
Up to eight Digital Clock Manager (DCM) modules
·
·
·
16 global clock multiplexer buffers in all parts
Fourth-generation segmented routing structure
Fast, predictable routing delay, independent of
fanout
Deep sub-micron noise immunity benefits
Up to 852 user I/Os
Twenty two single-ended standards and
five differential standards
Programmable LVTTL and LVCMOS sink/source
current (2 mA to 24 mA) per I/O
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
PCI support
Differential signaling
·
·
·
·
Proprietary high-performance SelectLink
technology for communications between Xilinx
devices
·
·
·
Precise clock de-skew
Flexible frequency synthesis
High-resolution phase shifting
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
Bus LVDS I/O
HyperTransport (LDT) I/O with current driver
buffers
Built-in DDR input and output registers
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
(1)
www.xilinx.com
1-800-255-7778
•
•
•
•
•
•
•
General Description
The Virtex-II Pro family is a platform FPGA for designs that
are based on IP cores and customized modules. The family
incorporates multi-gigabit transceivers and PowerPC CPU
cores in Virtex-II Pro Series FPGA architecture. It empow-
ers complete solutions for telecommunication, wireless, net-
working, video, and DSP applications.
The leading-edge 0.13µm CMOS nine-layer copper process
and the Virtex-II Pro architecture are optimized for high per-
formance designs in a wide range of densities. Combining a
wide variety of flexible features and IP cores, the
Virtex-II Pro family enhances programmable logic design
capabilities and is a powerful alternative to mask-pro-
grammed gate arrays.
SRAM-based in-system configuration
-
-
-
-
-
-
Supported by Xilinx Foundation™ and Alliance™
series development systems
-
-
0.13-µm, nine-layer copper process with 90 nm
high-speed transistors
1.5V (V
V
IEEE 1149.1 compatible boundary-scan logic support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
packages in standard 1.00 mm pitch
Each device 100% factory tested
CCAUX
Fast SelectMAP™ configuration
Triple Data Encryption Standard (DES) security
option (bitstream encryption)
IEEE1532 support
Partial reconfiguration
Unlimited reprogrammability
Readback capability
Integrated VHDL and Verilog design flows
ChipScope™ Integrated Logic Analyzer
CCINT
auxiliary and V
) core power supply, dedicated 2.5V
CCO
DS083-1 (v1.0) January 31, 2002
Advance Product Specification
I/O power supplies
R