XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 67
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XC2VP20-6FF1152C
Manufacturer Part Number
XC2VP20-6FF1152C
Description
Pro Platform FPGA
Manufacturer
Xilinx, Inc.
Datasheet
1.XC2VP20-6FF1152C.pdf
(268 pages)
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Table 22: Rocket I/O Transmitter Switching Characteristics
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
Notes:
1.
2.
Serial data rate, full-speed clock
Serial data rate, half-speed clock
Serial data output deterministic jitter
Serial data output random jitter
TX rise time
TX fall time
Transmit latency
TXUSRCLK duty cycle
TXUSRCLK2 duty cycle
UI = Unit Interval
Transmit latency delay from TXDATA to TXP/TXN
TXDATA[16:0]
TXUSRCLK2
R
TXP/TXN
Description
(2)
0
1
DATA ORIGINATES
2
Figure 3: Transmit Latency (Maximum, Including CRC)
. . . . .
Symbol
T
T
T
F
T
T
TX2DC
20
TXLAT
T
T
TXDC
GTX
RTX
FTX
DJ
RJ
1
21 22
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
1-800-255-7778
T
. . . . .
Wirebond packages
Wirebond packages
TXLAT
Flipchip packages
Flipchip packages
Excluding CRC
Including CRC
Conditions
20% – 80%
320
16
321 322
. . . . .
0.800
0.800
0.600
0.600
Min
45
45
340 341 342
Typ
17
120
120
DATA ARRIVES
50
50
14
8
DS083-3_03_082301
3.125
Max
0.18
0.17
2.5
1.0
1.0
17
11
55
55
. . . .
TXUSR
Units
cycles
Gb/s
Gb/s
Gb/s
Gb/s
CLK
UI
ps
ps
UI
%
%
(1)
67
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