XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 28

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
on the bank. These resistors, voltage reference of N transis-
tor (VRN) and the voltage reference of P transistor (VRP)
are shown in
When used with a terminated I/O standard, the value of the
resistors are specified by the standard (typically 50 ).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (20
tions listed in
must have the same value for any given bank. One percent
resistors are recommended.
The DCI system adjusts the I/O impedance to match the two
external reference resistors, or half of the reference resis-
tors, and compensates for impedance changes due to volt-
age and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
Controlled Impedance Drivers
(Series Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z
input buffers also support LVDCI and LVDCI_DV2 I/O stan-
dards.
28
Virtex-II Pro DCI
Z
Figure 18: Internal Series Termination
Figure 17: DCI in a Virtex-II Pro Bank
to 100
IOB
Figure
V
Table 8
1 Bank
CCO
DCI
DCI
DCI
DCI
= 3.3V, 2.5 V, 1.8 V, or 1.5 V
17.
. For all series and parallel termina-
and
VRN
VRP
Table
Z
V CCO
9, the reference resistors
GND
DS031_50_101200
R
R
REF
REF
(1%)
(1%)
0
). Virtex-II Pro
DS083-2_09_122001
www.xilinx.com
1-800-255-7778
Table 8: SelectI/O Controlled Impedance Buffers
Controlled Impedance Terminations
(Parallel Termination)
DCI also provides on-chip termination for SSTL3, SSTL2,
HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or
transmitters on bidirectional lines.
Table 9
Virtex-II Pro devices. V
Note that there is a V
GTLP_DCI, due to the on-chip termination resistor.
Table 9: SelectI/O Buffers With On-Chip Parallel
Termination
Notes:
1. SSTL Compatible
SSTL3 Class II
SSTL2 Class II
HSTL Class IV
SSTL3 Class I
SSTL2 Class I
HSTL Class III
HSTL Class II
I/O Standard
HSTL Class I
V
3.3V
2.5V
1.8V
1.5V
CCO
GTLP
GTL
lists the on-chip parallel terminations available in
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
DCI
CCO
Termination
HSTL_IV_18
HSTL_III_18
HSTL_II_18
CCO
HSTL_I_18
SSTL3_II
SSTL2_II
HSTL_IV
External
HSTL_III
SSTL3_I
SSTL2_I
HSTL_II
HSTL_I
GTLP
GTL
must be set according to
requirement for GTL_DCI and
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
DCI Half Impedance
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
HSTL_III_DCI_18
HSTL_IV_DCI_18
HSTL_II_DCI_18
SSTL3_II_DCI
SSTL2_II_DCI
HSTL_I_DCI_18
SSTL3_I_DCI
SSTL2_I_DCI
HSTL_IV_DCI
HSTL_III_DCI
HSTL_II_DCI
Termination
HSTL_I_DCI
N/A
GTLP_DCI
GTL_DCI
On-Chip
Table
(1)
(1)
(1)
(1)
5.
R