XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 19

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description:
PowerPC 405 Core
This section offers a brief overview of the various functional
blocks shown in
PPC405 Core
The PPC405 core is a 32-bit Harvard architecture proces-
sor. It consists of the following functional blocks as shown in
Figure
•
•
•
•
•
•
It operates on instructions in a five stage pipeline consisting
of a fetch, decode, execute, write-back, and load write-back
stage. Most instructions execute in a single cycle, including
loads and stores.
Instruction and Data Cache
The PPC405 core provides an instruction cache unit (ICU)
and a data cache unit (DCU) that allow concurrent accesses
and minimize pipeline stalls. The instruction and data cache
array are 16 KB each. Both cache units are two-way set
associative. Each way is organized into 256 lines of 32
bytes (eight words). The instruction set provides a rich
assortment of cache control instructions, including instruc-
tions to read tag information and data arrays.
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Cache units
Memory Management unit
Fetch Decode unit
Execution unit
Timers
Debug logic unit
7:
R
Figure
7.
PLB Master
PLB Master
Interface
Interface
D-Cache
I-Cache
Array
Array
Cache Units
Instruction
Cache
Cache
Data
Unit
Unit
Controller
Controller
D-Cache
I-Cache
Instruction
OCM
Data
OCM
Figure 7: PPC405 Core Block Diagram
Instruction Shadow
Data Shadow
Unified TLB
(64 Entry)
(8 Entry)
MMU
(4 Entry)
TLB
TLB
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The PPC405 core accesses external memory through the
instruction (ICU) and data cache units (DCU). The cache
units each include a 64-bit PLB master interface, cache
arrays, and a cache controller. The ICU and DCU handle
cache misses as requests over the PLB to another PLB
device such as an external bus interface unit. Cache hits are
handled as single cycle memory accesses to the instruction
and data caches.
Instruction Cache Unit (ICU)
The ICU provides one or two instructions per cycle to the
instruction queue over a 64-bit bus. A line buffer (built into
the output of the array for manufacturing test) enables the
ICU to be accessed only once for every four instructions, to
reduce power consumption by the array.
The ICU can forward any or all of the four or eight words of
a line fill to the EXU to minimize pipeline stalls caused by
cache misses. The ICU aborts speculative fetches aban-
doned by the EXU, eliminating unnecessary line fills and
enabling the ICU to handle the next EXU fetch. Aborting
abandoned requests also eliminates unnecessary external
bus activity, thereby increasing external bus utilization.
Data Cache Unit (DCU)
The DCU transfers one, two, three, four, or eight bytes per
cycle, depending on the number of byte enables presented
by the CPU. The DCU contains a single-element command
and store data queue to reduce pipeline stalls; this queue
enables the DCU to independently process load/store and
cache control instructions. Dynamic PLB request prioritiza-
tion reduces pipeline stalls even further. When the DCU is
busy with a low-priority request while a subsequent storage
Virtex-II Pro™ Platform FPGAs: Functional Description
Fetch & Decode
Execution Unit (EXU)
Decode
32 x 32
Execution Unit
Fetch
Logic
GPR
and
ALU
3-Element
(PFB1,
Queue
PFB0,
Fetch
DCD)
MAC
JTAG
Debug Logic
Watchdog)
Timers
Debug
Timers
(FIT,
PIT,
DS083-2_01_062001
&
Instruction
Trace
19