XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 86

no-image

XC2VP20-6FF1152C

Manufacturer Part Number
XC2VP20-6FF1152C
Description
Pro Platform FPGA
Manufacturer
Xilinx, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2VP20-6FF1152C
Manufacturer:
XILINX
Quantity:
210
Part Number:
XC2VP20-6FF1152C
Manufacturer:
XILINX
0
Part Number:
XC2VP20-6FF1152C
Manufacturer:
XILINX
Quantity:
50
Part Number:
XC2VP20-6FF1152CES
Manufacturer:
XILINX
0
DCM Timing Parameters
Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM
,
Table 43: Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM
DCM Timing Parameters
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605; all devices are
100% functionally tested. Because of the difficulty in directly
measuring many internal timing parameters, those parame-
ters are derived from benchmark timing patterns. The fol-
Operating Frequency Ranges
e
Table 44: Operating Frequency Ranges
86
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to
Global Clock Input Signal for
LVCMOS25 Standard.
For data input with different standards,
adjust the setup time delay by the values
shown in
Characteristics Standard
Adjustments, page
Full Delay
Global Clock and IFF without DCM
Output Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
IOB Input Switching
Description
Description
71.
CLKOUT_FREQ_1X_LF_MIN
CLKOUT_FREQ_1X_LF_MAX
CLKOUT_FREQ_2X_LF_MIN
CLKOUT_FREQ_2X_LF_MAX
CLKOUT_FREQ_DV_LF_MIN
CLKOUT_FREQ_DV_LF_MAX
CLKOUT_FREQ_FX_LF_MIN
CLKOUT_FREQ_FX_LF_MAX
T
PSFD
Symbol
Symbol
/T
www.xilinx.com
PHFD
1-800-255-7778
lowing guidelines reflect worst-case values across the
recommended operating conditions. All output jitter and
phase specifications are determined through statistical
measurement at the package pins.
XC2VP20
XC2VP50
XC2VP2
XC2VP4
XC2VP7
Device
Constraints
–8
-8
Speed Grade
Speed Grade
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
7
-7
6
-6
Units
Units
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
R

Related parts for XC2VP20-6FF1152C