XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 41

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

2. READ_FIRST
The READ_FIRST option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
memory also transfers the prior content of the memory cell
addressed into the data output registers DO, as shown in
Figure
3. NO_CHANGE
The NO_CHANGE option maintains the content of the out-
put registers, regardless of the write operation. The clock
edge during the write mode has no effect on the content of
the data output register DO. When the port is configured as
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
RAM Contents
RAM Contents
memory also transfers DI into the output registers DO,
as shown in
Data_out
Data_out
Address
Address
Data_in
Data_in
Data_in
Data_in
38.
CLK
CLK
WE
WE
R
Figure 37: WRITE_FIRST Mode
Figure 38: READ_FIRST Mode
Figure
DI
DI
New
New
Old
Old
aa
aa
Internal
Internal
Memory
Memory
37.
DO
DO
Prior stored data
Data_out = Data_in
New
New
New
Old
DS083-2_13_050901
DS083-2_14_050901
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NO_CHANGE, only a read operation loads a new value in
the output register DO, as shown in
Control Pins and Attributes
Virtex-II Pro SelectRAM memory has two independent
ports with the control signals described in
trol inputs including the clock have an optional inversion.
Table 18: Control Functions
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
Total Amount of SelectRAM Memory
Virtex-II Pro SelectRAM memory blocks are organized in
multiple columns. The number of blocks per column
depends on the row size, the number of Processor Blocks,
and the number of Rocket I/O transceivers.
Table 19
amount of block SelectRAM memory available for each
Virtex-II Pro device. The 18 Kb SelectRAM blocks are
cascadable to implement deeper or wider single- or dual-port
memory resources.
Virtex-II Pro™ Platform FPGAs: Functional Description
RAM Contents
Control Signal
Data_out
Address
Data_in
Data_in
SSR
CLK
WE
EN
CLK
WE
shows the number of columns as well as the total
Figure 39: NO_CHANGE Mode
DI
New
Old
aa
Read and Write Clock
Enable affects Read, Write, Set, Reset
Write Enable
Set DO register to SRVAL (attribute)
Internal
Memory
Last Read Cycle Content (no change)
DO
Function
Figure
No change during write
Table
New
39.
DS083-2_12_050901
18. All con-
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