XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 45

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

either input clock. As long as the presently selected clock is
High, any level change of S has no effect .
If the presently selected clock is Low while S changes, or if
it goes Low after S has changed, the output is kept Low until
the other ("to-be-selected") clock has made a transition
from High to Low. At that instant, the new clock starts driv-
ing the output.
The two clock inputs can be asynchronous with regard to
each other, and the S input can change at any time, except
for a short setup time prior to the rising edge of the presently
selected clock; that is, prior to the rising edge of the
BUFGMUX output O. Violating this setup time requirement
can result in an undefined runt pulse output.
All Virtex-II Pro devices have 16 global clock multiplexer
buffers.
Figure 49
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DS083-2 (v1.0) January 31, 2002
Advance Product Specification
CL K0
CLK1
Out
Figure 49: Clock Multiplexer Waveform Diagram
The current clock is CLK0.
S is activated High.
If CLK0 is currently High, the multiplexer waits for CLK0
to go Low.
Once CLK0 is Low, the multiplexer output stays Low
until CLK1 transitions High to Low.
When CLK1 transitions from High to Low, the output
switches to CLK1.
No glitches or short pulses can appear on the output.
S
Figure 48: Virtex-II Pro BUFGMUX Function
shows a switchover from CLK0 to CLK1.
R
Wait for Low
S
I
I
0
1
BUFGMUX
DS083-2_63_121701
Switch
O
DS083-2_46_121701
www.xilinx.com
1-800-255-7778
Digital Clock Manager (DCM)
The Virtex-II Pro DCM offers a wide range of powerful clock
management features.
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The DCM utilizes fully digital delay lines allowing robust
high-precision control of clock phase and frequency. It also
utilizes fully digital feedback systems, operating dynamically
to compensate for temperature and voltage variations dur-
ing operation.
Up to four of the nine DCM clock outputs can drive inputs to
global clock buffers or global clock multiplexer buffers simul-
taneously (see
taneously drive general routing resources, including routes
to output buffers.
The DCM can be configured to delay the completion of the
Virtex-II Pro configuration process until after the DCM has
achieved lock. This guarantees that the chip does not begin
operating until after the system clocks generated by the
DCM have stabilized.
The DCM has the following general control signals:
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Virtex-II Pro™ Platform FPGAs: Functional Description
Clock De-skew: The DCM generates new system
clocks (either internally or externally to the FPGA),
which are phase-aligned to the input clock, thus
eliminating clock distribution delays.
Frequency Synthesis: The DCM generates a wide
range of output clock frequencies, performing very
flexible clock multiplication and division.
Phase Shifting: The DCM provides both coarse phase
shifting and fine-grained phase shifting with dynamic
phase shift control.
RST input
LOCKED output pin: asserted High when all enabled
DCM circuits have locked.
STATUS output pins (active High): shown in
clock signal
control signal
Figure 50: Digital Clock Manager
pin:
Figure 50
resets the entire DCM
). All DCM clock outputs can simul-
RST
DSSEN
PSINCDEC
PSEN
CLKIN
CLKFB
PSCLK
DCM
STATUS[7:0]
CLK2X180
CLKFX180
PSDONE
LOCKED
CLK180
CLK270
CLKDV
CLKFX
CLK2X
CLK90
CLK0
DS031_67_112900
Table
21.
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