s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 134

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Serial Communications Interface (ESCI) Module
13.4 Interrupts
The following sources can generate ESCI interrupt requests:
13.4.1 Transmitter Interrupts
These conditions can generate interrupt requests from the ESCI transmitter:
13.4.2 Receiver Interrupts
These sources can generate interrupt requests from the ESCI receiver:
13.4.3 Error Interrupts
These receiver error flags in SCS1 can generate interrupt requests:
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2. Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the
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receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver
does not set the receiver idle bit, IDLE, or the ESCI receiver full bit, SCRF. The idle line type bit,
ILTY, determines whether the receiver begins counting 1s as idle character bits after the start bit
or after the stop bit.
ESCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred
a character to the transmit shift register. SCTE can generate a transmitter interrupt request. Setting
the ESCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter interrupt requests.
Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and
the SCDR are empty and that no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter interrupt
requests.
ESCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver interrupt request. Setting the
ESCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
interrupts.
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive 1s shifted in from the
RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate interrupt
requests.
Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate ESCI error interrupt requests.
Noise flag (NF) — The NF bit is set when the ESCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate ESCI error interrupt requests.
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle will cause the receiver to wake up.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
NOTE
Freescale Semiconductor