s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 211

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM2
channel 0 registers (T2CH0H:T2CH0L) initially control the buffered PWM output. TIM2 status control
register 0 (T2SCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority
over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM2 overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. See
17.4 Interrupts
The following TIM2 sources can generate interrupt requests:
17.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
17.5.1 Wait Mode
The TIM2 remains active after the execution of a WAIT instruction. In wait mode the TIM2 registers are
not accessible by the CPU. Any enabled interrupt request from the TIM2 can bring the MCU out of wait
mode.
If TIM2 functions are not required during wait mode, reduce power consumption by stopping the TIM2
before executing the WAIT instruction.
17.5.2 Stop Mode
The TIM2 module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. TIM2 operation resumes after an external interrupt. If stop mode is exited by
reset, the TIM2 is reset.
17.6 TIM2 During Break Interrupts
A break interrupt stops the counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data
Freescale Semiconductor
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TIM2 overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value
programmed in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable bit, TOIE,
enables TIM2 overflow interrupt requests. TOF and TOIE are in the T2SC register.
TIM2 channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM2 interrupt requests are controlled by the channel x interrupt
enable bit, CHxIE. Channel x TIM2 interrupt requests are enabled when CHxIE =1. CHxF and
CHxIE are in the T2SCx register.
17.8.1 TIM2 Status and Control
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
Register.
sheet.
Interrupts
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