s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 195

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

function, and TIM1 channel 1 status and control register (T1SC1) is unused. While the MS0B bit is set,
the channel 1 pin, T1CH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the T1CH2
pin. The TIM1 channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIM1 channel 2 status and control register (T1SC2) links channel 2 and channel 3.
The TIM1 channel 2 registers initially control the pulse width on the T1CH2 pin. Writing to the TIM1
channel 3 registers enables the TIM1 channel 3 registers to synchronously control the pulse width at the
beginning of the next PWM period. At each subsequent overflow, the TIM1 channel registers (2 or 3) that
control the pulse width are the ones written to last. T1SC2 controls and monitors the buffered PWM
function, and TIM1 channel 3 status and control register (T1SC3) is unused. While the MS2B bit is set,
the channel 3 pin, T1CH3, is available as a general-purpose I/O pin.
16.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
Freescale Semiconductor
1. In the TIM1 status and control register (T1SC):
2. In the TIM1 counter modulo registers (T1MODH:T1MODL), write the value for the required PWM
3. In the TIM1 channel x registers (T1CHxH:T1CHxL), write the value for the required pulse width.
4. In TIM1 channel x status and control register (T1SCx):
5. In the TIM1 status control register (T1SC), clear the TIM1 stop bit, TSTOP.
period.
a. Stop the counter by setting the TIM1 stop bit, TSTOP.
b. Reset the counter and prescaler by setting the TIM1 reset bit, TRST.
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on
or PWM signals) to the mode select bits, MSxB:MSxA. See
compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width level. See
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
NOTE
NOTE
Table
Table
16-2.
16-2.
Functional Description
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