s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 178

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI) Module
15.3.5 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is 0.
Whenever SPE is 0, the following occurs:
These items are reset only by a system reset:
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without
having to set all control bits again when SPE is set high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the
SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be
disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
15.3.6 Error Conditions
The following flags signal SPI error conditions:
15.3.6.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous
transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe
occurs in the middle of SPSCK cycle 7 (see
received after the overflow and before the OVRF bit is cleared does not transfer to the receive data
register and does not set the SPI receiver full bit (SPRF). The unread data that transferred to the receive
data register before the overflow occurred can still be read. Therefore, an overflow error always indicates
the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading
the SPI data register.
OVRF generates a receiver/error interrupt request if the error interrupt enable bit (ERRIE) is also set. The
SPRF, MODF, and OVRF interrupts share the same interrupt vector (see
to enable MODF or OVRF individually to generate a receiver/error interrupt request. However, leaving
MODFEN low prevents MODF from being set.
If the SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.
Figure 15-9
possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by
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The SPTE flag is set.
Any transmission currently in progress is aborted.
The shift register is cleared.
The SPI state counter is cleared, making it ready for a new complete transmission.
All the SPI pins revert back to being general-purpose I/O.
All control bits in the SPCR register
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
The status flags SPRF, OVRF, and MODF
Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift
register sets the OVRF bit. The new byte does not transfer to the receive data register, and the
unread byte still can be read. OVRF is in the SPI status and control register.
Mode fault error (MODF) — The MODF bit indicates that the voltage on the slave select pin (SS)
is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
shows how it is possible to miss an overflow. The first part of
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
Figure 15-4
and
Figure
15-6.) If an overflow occurs, all data
Figure
Figure 15-9
15-11.) It is not possible
Freescale Semiconductor
shows how it is