s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 49

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case
that the conversion was aborted by a reset, ADRH and ADRL return to their reset states.
Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive
state. In this state, all internal clocks and references are disabled. This state is entered asynchronously
and immediately upon aborting of a conversion.
3.3.3.4 Total Conversion Time
The total conversion time depends on many factors such as sample time, bus frequency, whether
ACLKEN is set, and synchronization time. The total conversion time is summarized in
The maximum total conversion time for a single conversion or the first conversion in continuous
conversion mode is determined by the clock source chosen and the divide ratio selected. The clock
source is selectable by ADICLK and ACLKEN, and the divide ratio is specified by ADIV. For example, if
the alternative clock source is 16 MHz and is selected as the input clock source, the input clock
divide-by-8 ratio is selected and the bus frequency is 4 MHz, then the conversion time for a single 10-bit
conversion is:
Freescale Semiconductor
8-Bit Mode (short sample — ADLSMP = 0):
8-Bit Mode (long sample — ADLSMP = 1):
10-Bit Mode (short sample — ADLSMP = 0):
10-Bit Mode (long sample — ADLSMP = 1):
Conversion time =
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
The ADCK frequency must be between f
maximum to meet A/D specifications.
Number of bus cycles = 11.25 µs x 4 MHz = 45 cycles
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
Table 3-1. Total Conversion Time versus Control Conditions
Conversion Mode
21 ADCK cycles
Bus
Bus
Bus
Bus
16 MHz/8
≥ f
≥ f
≥ f
≥ f
ADCK
ADCK
ADCK
ADCK
)
)
)
)
NOTE
+
3 bus cycles
ACLKEN
ADCK
4 MHz
X
X
X
X
0
1
0
1
0
1
0
1
minimum and f
18 ADCK + 3 bus clock + 5 µs
38 ADCK + 3 bus clock + 5 µs
21 ADCK + 3 bus clock + 5 µs
41 ADCK + 3 bus clock + 5 µs
Maximum Conversion Time
= 11.25 µs
18 ADCK + 3 bus clock
38 ADCK + 3 bus clock
21 ADCK + 3 bus clock
41 ADCK + 3 bus clock
ADCK
16 ADCK
36 ADCK
19 ADCK
39 ADCK
Functional Description
Table
3-1.
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