s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 209

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

$00FF (255) to the TIM2 counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is 000. See
The value in the TIM2 channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM2 channel registers
produces a duty cycle of 128/256 or 50%.
17.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in
Modulation
pulse width value over the old value currently in the TIM2 channel registers.
An unsynchronized write to the TIM2 channel registers to change a pulse width value could cause
incorrect operation for up to two PWM periods. For example, writing a new value before the counter
reaches the old value but after the counter reaches the new value prevents any compare during that PWM
period. Also, using a TIM2 overflow interrupt routine to write a new, smaller pulse width value may cause
the compare to be missed. The TIM2 may pass the new value before it is written to the timer channel
(T2CHxH:T2CHxL).
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
Freescale Semiconductor
•
•
When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
When changing to a longer pulse width, enable TIM2 overflow interrupts and write the new value
in the TIM2 overflow interrupt routine. The TIM2 overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current
pulse) could cause two output compares to occur in the same PWM period.
(PWM). The pulses are unbuffered because changing the pulse width requires writing the new
POLARITY = 1
POLARITY = 0
(ELSxA = 0)
(ELSxA = 1)
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
T2CHx
T2CHx
OVERFLOW
Figure 17-3. PWM Period and Pulse Width
PULSE
WIDTH
PERIOD
COMPARE
OUTPUT
OVERFLOW
NOTE
17.8.1 TIM2 Status and Control
COMPARE
OUTPUT
OVERFLOW
Functional Description
17.3.4 Pulse Width
Register.
COMPARE
OUTPUT
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