s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 164

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
14.6.4 Break Interrupts
The break module can stop normal program flow at a software programmable break point by asserting its
break interrupt output. (See
Chapter 18 Development
Support.) The SIM puts the CPU into the break
state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to
see how each module is affected by the break state.
14.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
14.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power- consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing
interrupts to occur.
14.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run.
Figure 14-14
shows
the timing for wait mode entry.
ADDRESS BUS
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
DATA BUS
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 14-14. Wait Mode Entry Timing
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if
the module is active or inactive in wait mode. Some modules can be programmed to be active in wait
mode.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
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Freescale Semiconductor