s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 196

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM1)
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM1
channel 0 registers (T1CH0H:T1CH0L) initially control the buffered PWM output. TIM1 status control
register 0 (T1SC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority
over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIM1
channel 2 registers (T1CH2H:T1CH2L) initially control the buffered PWM output. TIM1 status control
register 2 (T1SC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority
over MS2A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM1 overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. See
16.4 Interrupts
The following TIM1 sources can generate interrupt requests:
16.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
16.5.1 Wait Mode
The TIM1 remains active after the execution of a WAIT instruction. In wait mode the TIM1 registers are
not accessible by the CPU. Any enabled interrupt request from the TIM1 can bring the MCU out of wait
mode.
If TIM1 functions are not required during wait mode, reduce power consumption by stopping the TIM1
before executing the WAIT instruction.
16.5.2 Stop Mode
The TIM1 module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. TIM1 operation resumes after an external interrupt. If stop mode is exited by
reset, the TIM1 is reset.
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TIM1 overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value
programmed in the TIM1 counter modulo registers. The TIM1 overflow interrupt enable bit, TOIE,
enables TIM1 overflow interrupt requests. TOF and TOIE are in the T1SC register.
TIM1 channel flags (CH3F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM1 interrupt requests are controlled by the channel x interrupt
enable bit, CHxIE. Channel x TIM1 interrupt requests are enabled when CHxIE =1. CHxF and
CHxIE are in the T1SCx register.
16.8.4 TIM1 Channel Status and Control
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
Registers.
Freescale Semiconductor