s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 217

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s908qc16vdse

Manufacturer Part Number
s908qc16vdse
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
TOVx — Toggle-On-Overflow Bit
CHxMAX — Channel x Maximum Duty Cycle Bit
Freescale Semiconductor
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the counter overflows. When channel x is an input capture channel, TOVx has no effect.
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
1 = Channel x pin toggles on TIM2 counter overflow.
0 = Channel x pin does not toggle on TIM2 counter overflow.
MSxB
X
X
0
0
0
0
0
0
0
1
1
1
After initially enabling a TIM2 channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
When TOVx is set, a counter overflow takes precedence over a channel x
output compare if both occur at the same time.
T2CHx
CHxMAX
MSxA
X
X
X
0
1
0
0
0
1
1
1
1
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
OVERFLOW
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
Table 17-2. Mode, Edge, and Level Selection
Figure 17-11
COMPARE
PERIOD
OUTPUT
ELSxA
Figure 17-11. CHxMAX Latency
0
0
1
0
1
0
1
0
1
1
0
1
OVERFLOW
Output compare
shows, the CHxMAX bit takes effect in the cycle after it is set
Buffered output
buffered PWM
Output preset
Input capture
COMPARE
OUTPUT
compare or
or PWM
Mode
NOTE
NOTE
OVERFLOW
COMPARE
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
OUTPUT
OVERFLOW
COMPARE
Configuration
OUTPUT
OVERFLOW
Registers
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