s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 162

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
14.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
14.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources.
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
162
Priority
Highest
Lowest
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
Reset
SWI instruction
IRQ pin
TIM1 channel 0 interrupt
TIM1 channel 1 interrupt
TIM1 overflow interrupt
TIM1 channel 2 vector
TIM1 channel 3 vector
ESCI error vector
ESCI receive vector
ESCI transmit vector
SPI receive
SPI transmit
Keyboard interrupt
ADC conversion complete interrupt
TIM2 channel 0 interrupt flag
TIM2 channel 1 interrupt flag
TIM2 overflow interrupt flag
Periodic wakeup interrupt flag
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
Source
Table 14-3. Interrupt Sources
SPRF, OVRF, MODF
SCTE, TC
OR, HF,
FE, PE
COCO
PWUF
SCRF
CH0F
CH1F
CH2F
CH3F
SPTE
KEYF
CH0F
CH1F
IRQF
Flag
TOF
TOF
NOTE
—
—
SPRIE, ERRIE
SCTIE, TCIE
ORIE, NEIE,
FEIE, PEIE
TOIEINT
IMASKK
Mask
PWUIE
IMASK
SCRIE
CH0IE
CH1IE
CH2IE
CH3IE
CH0IE
CH1IE
SPTIE
TOIE
AIEN
—
—
(1)
Register Flag
Table 14-3
IF10
IF11
IF12
IF13
IF14
IF15
IF16
IF17
IF18
IF19
INT
IF1
IF3
IF4
IF5
IF6
IF7
IF9
—
—
Freescale Semiconductor
summarizes the
$FFDC–$FFDD
$FFDA–$FFDB
$FFFC–$FFFD
$FFEE–$FFEF
$FFEA–$FFEB
$FFDE–$FFDF
$FFFE–$FFFF
$FFFA–$FFFB
$FFD8–$FFD9
$FFD6–$FFD7
$FFE8–$FFE9
$FFE6–$FFE7
$FFE4–$FFE5
$FFE2–$FFE3
$FFE0–$FFE1
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFF0–$FFF1
Address
Vector