mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 122

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Notes
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
10.
1. All voltages are referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e.,
6. There are two sets of values listed for Command/Address:
7. The values listed are for the differential DQS strobe (DQS and DQS#) with a differen-
8.
9. This maximum value is derived from the referenced test load.
Output
(V
OUT
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified. ODT is disabled for all
measurements that are not ODT-specific.
ment and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The slew rate for the input signals used to test the
device is 1.0 V/ns for signals in the range between V
other than 1.0 V/ns may require the timing parameters to be derated as specified.
the receiver will effectively switch as a result of the signal crossing the AC input level
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
t
at V
defined values, referenced from the logic trip points.
for a rising signal and V
for a rising signal and V
not equal to 1 V/ns, then the baseline values must be derated by adding the values
from Tables 27 and 28 on page 89.
tial slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed:
t
baseline values of
baseline values,
trip points.
signal, while
ing signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline val-
ues must be derated by adding the values from Tables 29 and 30 on pages 94–95. If the
DQS differential strobe feature is not enabled, then the DQS strobe is single-ended,
the baseline values not applicable, and timing is not referenced to the logic trip
points. Single-ended DQS data timing is referenced to DQS crossing V
timing values for a single-ended DQS strobe are listed in Tables 31–34 on pages 96–97;
listed values are already derated for slew rate variations and can be used directly from
the table.
t
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (
over
t
IS
DH
HZ and
LZ (MIN) will prevail over a
a
)
V
,
REF
a
TT =
t
t
IH
DQSCK (MAX) +
and
when the slew rate is 1 V/ns. The baseline values,
a
V
t
values (for reference only) are equivalent to the baseline values of
LZ transitions occur in the same access time windows as valid data transi-
DD
t
25Ω
DS
Reference
Point
Q/2
t
DS
t
b
DH
,
b
t
DD
DH
t
is referenced from V
DS
b
t
is referenced from V
tests may use a V
DS
b
b
DD
. The
,
b
t
t
DH
,
RPST (MAX) condition.
IH
IL
, and electrical AC and DC characteristics may be conducted
t
DH
(
(
AC
DC
t
b
122
DS
, are the JEDEC-defined values, referenced from the logic
b
) for a falling signal, while
t
) for a falling signal. If the Command/Address slew rate is
DQSCK (MIN) +
a
at V
,
SS
t
DH
.
REF
a
IL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
when the slew rate is 2 V/ns, differentially. The
IH
values (for reference only) are equivalent to the
-to-V
IL
(
AC
(
DC
) for a rising signal and V
IH
) for a rising signal and V
2Gb: x4, x8, x16 DDR2 SDRAM
t
swing of up to 1.0V in the test environ-
HZ) or begins driving (
t
RPRE (MAX) condition.
IL
t
(
IS
AC
t
IH
b
) and V
t
is referenced from V
b
IS
t
IS
is referenced from V
b
©2006 Micron Technology, Inc. All rights reserved.
a
,
,
t
t
IH
t
HZ (MAX) will prevail
IH
IH
b
(
a
, are the JEDEC-
AC
IL
and
t
(
). Slew rates
IH
LZ).
AC
REF
(
t
DC
) for a falling
IS
. The correct
b
) for a fall-
,
t
IS
t
IH
IH
b
Notes
,
b
(
IL
t
. The
AC
t
IH
DS
(
DC
)
b
a
)
,