mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 34

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 8:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
Minimum Delay with Auto Precharge Enabled
10. The number of clock cycles required to meet
4. REFRESH and LM commands may only be issued when all banks are idle.
5. Not used.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
8. Requires appropriate DM.
9. A WRITE command may be applied after the completion of the READ burst.
From Command
WRITE with auto
READ with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
greater.
precharge
precharge
(Bank n)
READ with
auto
precharge
enabled/
WRITE with
auto
precharge
enabled:
The minimum delay from a READ or WRITE command with auto precharge
enabled to a command to a different bank is summarized in Table 8:
The READ with auto precharge enabled or WRITE with auto precharge
enabled states can each be broken into two parts: the access period and
the precharge period. For READ with auto precharge, the precharge period
is defined as if the same burst was executed with auto precharge disabled
and then followed with the earliest possible PRECHARGE command that
still accesses all of the data in the burst. For WRITE with auto precharge,
the precharge period begins when
precharge was disabled. The access period starts with registration of the
command and ends where the precharge period (or
supports concurrent auto precharge such that when a READ with auto
precharge is enabled or a WRITE with auto precharge is enabled, any
command to other banks is allowed, as long as that command does not
interrupt the read or write data transfer already in process. In either case,
all other related limitations apply (contention between read data and
write data must be avoided).
WRITE or WRITE with auto
WRITE or WRITE with auto
To Command (Bank m)
READ or READ with auto
READ or READ with auto
PRECHARGE or ACTIVE
PRECHARGE or ACTIVE
precharge
precharge
precharge
precharge
34
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t
WTR is either 2 or
2Gb: x4, x8, x16 DDR2 SDRAM
t
WR ends, with
(CL - 1) + (BL / 2) +
(with concurrent
Minimum Delay
auto precharge)
Command Truth Tables
(BL / 2) + 2
©2006 Micron Technology, Inc. All rights reserved.
(BL / 2)
(BL / 2)
t
WTR/
t
1
1
WR measured as if auto
t
RP) begins. This device
t
CK, whichever is
t
WTR
Units
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK