mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 59

no-image

mt47h128m16hg-3-it

Manufacturer Part Number
mt47h128m16hg-3-it
Description
2gb X4, X8, X16 Ddr2 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
Figure 43:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
Data Input Timing
Notes:
DQS#
1.
2.
3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
5. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
6. Subsequent rising DQS signals must align to the clock within
DQS
CK#
DM
DQ
CK
t
t
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
T0
WL -
t
DQSS (NOM)
T1
59
T1n
t WPRE
t
t
DQSS (MAX).
DQSS (MIN).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
DI
t DSH 1
TRANSITIONING DATA
T2n
t DQSL
2Gb: x4, x8, x16 DDR2 SDRAM
t DSS 2
T3
6
t DQSH t WPST
t DSH 1
T3n
t
DQSS.
t DSS 2
©2006 Micron Technology, Inc. All rights reserved.
T4
WRITE Command
DON’T CARE

Related parts for mt47h128m16hg-3-it