mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 48

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 31:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
LDQS#/LDQS / UDQ#/UDQS 2
All DQs, collectively 3
DQ (Last data valid)
DQ (First data valid)
DQS#/DQS, or
Data Output Timing –
Notes:
CK#
CK
T0 7
1.
2. DQ transitioning after DQS transitions define
3. All DQ must transition by
4.
5.
6.
7. READ command with CL = 3, AL = 0 issued at T0.
8. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,
t
skew.
t
t
t
but to when the device begins to drive or no longer drives, respectively.
DQSCK is the DQS output window relative to CK and is the “long-term” component of DQS
AC is the DQ output window relative to CK and is the “long term” component of DQ skew.
LZ (MIN) and
HZ (MAX) and
T1
t
AC and
t LZ (MIN)
t
AC (MIN) are the first valid signal transitions.
t
AC (MAX) are the latest valid signal transitions.
T2
t
DQSCK
t LZ (MIN)
t RPRE
t
DQSQ after DQS transitions, regardless of
48
T3
t DQSCK 1 (MIN)
T3
T3
T3
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
T3n
T3n
t AC 4 (MIN)
T4
t
DQSQ window.
2Gb: x4, x8, x16 DDR2 SDRAM
T4
T4
T4
T4n
T4n
T4n
T4n
t AC 4 (MAX)
T5
T5
T5
T5
©2006 Micron Technology, Inc. All rights reserved.
T5n
t DQSCK 1 (MAX)
T5n
T5n
T5n
READ Command
t
AC.
T6
T6
T6
T6
t HZ (MAX)
t HZ (MAX)
T6n
t RPST
T6n
T6n
T6n
T7