mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 14

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

BA0–BA2
Functional Description
Figure 4:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
A0–A13,
RAS#
CAS#
WE#
ODT
CKE
CK#
CS#
CK
18
ADDRESS
REGISTER
REGISTERS
MODE
CONTROL
Functional Block Diagram – 128 Meg x 16
LOGIC
18
COUNTER
REFRESH
14
10
3
14
The 2Gb DDR2 SDRAM is a high-speed CMOS dynamic random access memory
containing 2,147,483,648 bits. The 2Gb DDR2 SDRAM is internally configured as an 8-
bank DRAM.
The 2Gb DDR2 SDRAM uses a double data rate architecture to achieve high-speed oper-
ation. The DDR2 architecture is essentially a 4n-prefetch architecture, with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or write
access for the 2Gb DDR2 SDRAM consists of a single 4n-bit-wide, one-clock-cycle data
transfer at the internal DRAM core and four corresponding n-bit- wide, one-half-clock-
cycle data transfers at the I/O balls.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Figure 7 on page 16 shows a simplified state diagram to provide the basic command flow.
It is not comprehensive and does not identify all timing requirements or possible
command restrictions.
ADDRESS
ROW-
2
MUX
CONTROL
13
COUNTER/
LOGIC
COLUMN-
BANK
ADDRESS
LATCH
DECODER
ADDRESS
BANK 0
LATCH
ROW-
BANK 1
&
BANK 2
BANK 3
BANK 4
8
2
16,324
BANK 5
BANK 6
BANK 7
DM MASK LOGIC
(16,324 x 256 x 64)
I/O GATING
SENSE AMPLIFIERS
DECODER
COLUMN
16,384
MEMORY
(x64)
BANK 0
256
ARRAY
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
14
COL0,COL1
CK,CK#
64
64
64
LATCH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
READ
CK OUT
DRIVERS
WRITE
CK IN
FIFO
&
16
16
16
16
MASK
DATA
COL0,COL1
8
64
MUX
2Gb: x4, x8, x16 DDR2 SDRAM
GENERATOR
2
2
2
2
16
16
16
16
REGISTERS
DQS
INPUT
DATA
16
UDQS, UDQS#
LDQS, LDQS#
2
2
2
16
16
16
16
2
4
16
CK,CK#
2
Functional Description
DRVRS
4
DLL
RCVRS
©2006 Micron Technology, Inc. All rights reserved.
sw1 sw2
sw1 sw2
sw1 sw2
sw1 sw2
R1
R1
R1
R1
R1
R1
ODT CONTROL
R2
R2
R2
R2
R2
R2
VssQ
sw3
sw3
sw3
sw3
R3
R3
R3
R3
R3
R3
V
DD
Q
UDQS, UDQS#
LDQS, LDQS#
DQ0–DQ15
UDM, LDM